aboutsummaryrefslogtreecommitdiff
path: root/target-arm/helper.c
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2014-05-01 15:24:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-01 15:24:44 +0100
commit3b7715796401ad1b00f752217fe8f425915e801b (patch)
treee45b953a40a49d6ddea723481bd7acef9a66d2d6 /target-arm/helper.c
parent051b9980b99dbfba22ea5f79bd3708d513ae121d (diff)
target-arm: Implement XScale cache lockdown operations as NOPs
XScale defines some implementation-specific coprocessor registers for doing cache lockdown operations. Since QEMU doesn't model a cache no proper implementation is possible, but NOP out the registers so that guest code like u-boot that tries to use them doesn't crash. Reported-by: <prqek@centrum.cz> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
-rw-r--r--target-arm/helper.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 43c1b4f01d..7c083c33a0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1578,6 +1578,21 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
.resetvalue = 0, },
+ /* XScale specific cache-lockdown: since we have no cache we NOP these
+ * and hope the guest does not really rely on cache behaviour.
+ */
+ { .name = "XSCALE_LOCK_ICACHE_LINE",
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "XSCALE_UNLOCK_ICACHE",
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "XSCALE_DCACHE_LOCK",
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_NOP },
+ { .name = "XSCALE_UNLOCK_DCACHE",
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};