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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-23 15:36:44 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 15:09:41 +0000 |
| commit | 52ff951b4f63a29593650a15efdf82f63d6d962d (patch) | |
| tree | 3008f7378ae5c4678222ada18c3d3f9eb2e9a074 /target-arm/helper.c | |
| parent | cb01d3912c8b000ed26d5fe95f6c194b3e3ba7a6 (diff) | |
target-arm: Add comment about not implementing NSACR.RFR
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index b2d2440edd..57cc8790c8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5214,6 +5214,9 @@ static int bad_mode_switch(CPUARMState *env, int mode) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: + /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + */ return 0; case ARM_CPU_MODE_MON: return !arm_is_secure(env); |