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authorAlex Bennée <alex.bennee@linaro.org>2014-03-17 16:31:48 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-17 16:31:48 +0000
commitb05c3068577f6caea6f1911b9e03d52dbf84f475 (patch)
tree4c54b6b2380736b33e39dcd4dbedd9f51fd7ed93 /target-arm/helper-a64.c
parentf612537e0706761d5692deaa72516695ef0a2ac8 (diff)
target-arm: A64: Add remaining CLS/Z vector ops
Implement the CLS, CLZ operations in the 2-reg-misc category. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper-a64.c')
-rw-r--r--target-arm/helper-a64.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 80ed029053..8f53223cee 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -60,6 +60,11 @@ uint32_t HELPER(cls32)(uint32_t x)
return clrsb32(x);
}
+uint32_t HELPER(clz32)(uint32_t x)
+{
+ return clz32(x);
+}
+
uint64_t HELPER(rbit64)(uint64_t x)
{
/* assign the correct byte position */