aboutsummaryrefslogtreecommitdiff
path: root/target-arm/cpu.h
diff options
context:
space:
mode:
authorFabian Aggeler <aggelerf@ethz.ch>2014-12-11 12:07:50 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-12-11 12:07:50 +0000
commit6e8801f9dea9e10449f4fd7d85dbe8cab708a686 (patch)
treea5ef60f3661ba2ba765380f561ff05ce5ff1fba3 /target-arm/cpu.h
parent137feaa9a1622620adf19c0b707883dd990738e2 (diff)
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-15-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
0 files changed, 0 insertions, 0 deletions