diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
| commit | 34222fb8101298ead0e43766340843b469597580 (patch) | |
| tree | 8af1e731cf56afb37c46b7236964b287a3924d23 /target-arm/cpu.h | |
| parent | 9cfa0b4e4c3076683b6c528a1a3b43d5a202a497 (diff) | |
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 67e935df42..328c256c3e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -172,7 +172,7 @@ typedef struct CPUARMState { uint32_t c0_cpuid; uint64_t c0_cssel; /* Cache size selection. */ uint64_t c1_sys; /* System control register. */ - uint32_t c1_coproc; /* Coprocessor access register. */ + uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ |