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authorPeter Maydell <peter.maydell@linaro.org>2012-07-12 10:59:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-07-12 10:59:54 +0000
commitde9b05b807918d40db9e26ddd6a54ad2978ac5b7 (patch)
treec9518ecd83f855a85dc9ae6099ca0ffa65379512 /target-arm/cpu.h
parent3cc0cd61f4adfecf2c0de392fe61a7e323e496ba (diff)
target-arm: Implement privileged-execute-never (PXN)
Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index aadfca0a26..82cad4b975 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -386,6 +386,8 @@ enum arm_features {
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
+ ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
+ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
};
static inline int arm_feature(CPUARMState *env, int feature)