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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:05 +0100 |
| commit | f32cdad55de242a23aae9842cdb659e6de116352 (patch) | |
| tree | bc79b7f88127ad260932de5f3cda6da57fd2644d /target-arm/cpu.h | |
| parent | 9449fdf61fc32e50e29d9bc5b531f1d238c13c97 (diff) | |
target-arm: Implement auxiliary fault status registers
Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
0 files changed, 0 insertions, 0 deletions