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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:52 +0100
commit1b1742386c82541d65a5068d9d5da42c3b4f61a5 (patch)
treeee4297028eed4c6b99ca02a32706020c386abff8 /target-arm/cpu.h
parent73fb3b764b076132fb269475c128a7e9dcb22ed6 (diff)
target-arm: A64: Add ELR entries for EL2 and 3
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ba1d495be5..60414ac088 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -162,7 +162,7 @@ typedef struct CPUARMState {
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
- uint64_t elr_el[2]; /* AArch64 exception link regs */
+ uint64_t elr_el[4]; /* AArch64 exception link regs */
uint64_t sp_el[4]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */