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authorPeter Maydell <peter.maydell@linaro.org>2011-07-20 10:32:55 +0000
committerPeter Maydell <peter.maydell@linaro.org>2011-07-26 14:30:54 +0000
commit906879a98fa31232f494fece3c5cb3c2baaf8c3c (patch)
tree40d311303266cc8e8004b69c6f81d2766bab59bb /target-arm/cpu.h
parent7807eed932dbb88fa320ddba99bff45ba96319c6 (diff)
target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such, thus enabling the TLS registers, NOP hints, CLREX, half and byte wide exclusive load/stores, etc. The VA-to-PA translation registers are not present on 1136r1, so introduce a new feature flag for them, which is enabled on 1176, 11MPCore and all v7 cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 8da3ff41ac..c28f767051 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -374,6 +374,7 @@ enum arm_features {
ARM_FEATURE_V4T,
ARM_FEATURE_V5,
ARM_FEATURE_STRONGARM,
+ ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
};
static inline int arm_feature(CPUARMState *env, int feature)