diff options
| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-12-11 12:07:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:50 +0000 |
| commit | 137feaa9a1622620adf19c0b707883dd990738e2 (patch) | |
| tree | c5eacacf5f85cf7cb1772fc18e20f27d057b639f /target-arm/cpu.h | |
| parent | e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 (diff) | |
target-arm: add SCTLR_EL3 and make SCTLR banked
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-14-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cdf2dd7349..6559aa8e61 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -178,7 +178,15 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint64_t c0_cssel; /* Cache size selection. */ - uint64_t c1_sys; /* System control register. */ + union { /* System control register. */ + struct { + uint64_t _unused_sctlr; + uint64_t sctlr_ns; + uint64_t hsctlr; + uint64_t sctlr_s; + }; + uint64_t sctlr_el[4]; + }; uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ |