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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:51 +0100
commit6947f05978806a7066fcaeccd8c187d577677328 (patch)
tree0f5fb285f320ef2ef4a5f369a51487ac3bf2da3f /target-arm/cpu.h
parentf79fbf39e266e6fef3d796ef3884aefb9506b73c (diff)
target-arm: Make elr_el1 an array
No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5aa978d9cd..fabfe9ecbb 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -162,7 +162,7 @@ typedef struct CPUARMState {
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
- uint64_t elr_el1; /* AArch64 ELR_EL1 */
+ uint64_t elr_el[2]; /* AArch64 exception link regs */
uint64_t sp_el[2]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */