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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:06 +0100 |
| commit | 19525524a755a98f72b80c92c4f6bdeea3002da5 (patch) | |
| tree | 3c5c7f0f62b438acac3d4cbc143c7707c1b33c76 /target-arm/cpu.h | |
| parent | f32cdad55de242a23aae9842cdb659e6de116352 (diff) | |
target-arm: Implement AArch64 address translation operations
Implement the AArch64 address translation operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d0f42fd72a..bebb333381 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -188,8 +188,7 @@ typedef struct CPUARMState { uint64_t esr_el1; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el1; /* Fault address registers. */ - uint32_t c7_par; /* Translation result. */ - uint32_t c7_par_hi; /* Translation result, high 32 bits */ + uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c9_pmcr; /* performance monitor control register */ |