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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2006-10-22 11:54:30 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2006-10-22 11:54:30 +0000
commitd37aca662561a54a5ea177c6c05280633fa41cb8 (patch)
tree2ec3f81972d17571e8fb1b9b802270433c1173e1 /target-arm/cpu.h
parente6e5906b6e0a81718066ca43aef57515026c6624 (diff)
Fix comment typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2197 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 75a1f1314b..b994bdd29a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -48,7 +48,7 @@ typedef struct CPUARMState {
/* Regs for current mode. */
uint32_t regs[16];
/* Frequently accessed CPSR bits are stored separately for efficiently.
- This contains all the other bits. Use cpsr_{read,write} to accless
+ This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
uint32_t spsr;