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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-07-29 17:57:26 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-07-29 17:57:26 +0000
commitc3d2689d88159291ef8af338b5f01cfbe5551d2c (patch)
tree814183cc0c4631b3762355f4e48fe77b1c3654ff /target-arm/cpu.h
parenta5236105dbf7b971715f1ac55f52f716081a0632 (diff)
Basic OMAP310 support. Basic Palm Tungsten|E machine emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5bd40ffbc4..ef203c3315 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -99,6 +99,10 @@ typedef struct CPUARMState {
uint32_t c13_fcse; /* FCSE PID. */
uint32_t c13_context; /* Context ID. */
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
+ uint32_t c15_ticonfig; /* TI925T configuration byte. */
+ uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
+ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
+ uint32_t c15_threadid; /* TI debugger thread-ID. */
} cp15;
/* Coprocessor IO used by peripherals */
@@ -247,7 +251,8 @@ enum arm_features {
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
- ARM_FEATURE_MPU /* Only has Memory Protection Unit, not full MMU. */
+ ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
+ ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -265,6 +270,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1026 0x4106a262
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_ARM946 0x41059461
+#define ARM_CPUID_TI915T 0x54029152
+#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPUID_PXA250 0x69052100
#define ARM_CPUID_PXA255 0x69052d00
#define ARM_CPUID_PXA260 0x69052903