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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-08-04 14:41:55 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-08-04 14:41:55 +0100
commitf2c30f42f506ea884de22f79d9da43867a327b2a (patch)
tree60246b31064beb7ddbdeb0fa9d517bedb4f61ef1 /target-arm/cpu.h
parent2f0180c51bfbd00b35d02149b831734f04c12d44 (diff)
target-arm: Add ESR_EL2 and 3
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b755f99e64..3d9cf576f6 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -185,7 +185,7 @@ typedef struct CPUARMState {
uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
uint32_t ifsr_el2; /* Fault status registers. */
- uint64_t esr_el[2];
+ uint64_t esr_el[4];
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[2]; /* Fault address registers. */
uint64_t par_el1; /* Translation result. */