diff options
| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-08 02:30:40 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-08 02:30:40 +0000 |
| commit | ce8198612e08f737057d9984a9fa1bf18af8ce4b (patch) | |
| tree | 73a22b7f00ad045b102c0dc53df6d6ef20396597 /target-arm/cpu.h | |
| parent | 945545501641bad0b650350168e365eff9a3eef3 (diff) | |
ARM946 CPU support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2783 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 09083b723a..4723807626 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -83,10 +83,14 @@ typedef struct CPUARMState { uint32_t c0_cachetype; uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ - uint32_t c2; /* MMU translation table base. */ - uint32_t c3; /* MMU domain access control register. */ + uint32_t c2_base; /* MMU translation table base. */ + uint32_t c2_data; /* MPU data cachable bits. */ + uint32_t c2_insn; /* MPU instruction cachable bits. */ + uint32_t c3; /* MMU domain access control register + MPU write buffer control. */ uint32_t c5_insn; /* Fault status registers. */ uint32_t c5_data; + uint32_t c6_region[8]; /* MPU base/size registers. */ uint32_t c6_insn; /* Fault address registers. */ uint32_t c6_data; uint32_t c9_insn; /* Cache lockdown registers. */ @@ -241,7 +245,8 @@ enum arm_features { ARM_FEATURE_VFP, ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ - ARM_FEATURE_IWMMXT /* Intel iwMMXt extension. */ + ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ + ARM_FEATURE_MPU /* Only has Memory Protection Unit, not full MMU. */ }; static inline int arm_feature(CPUARMState *env, int feature) @@ -258,6 +263,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM1026 0x4106a262 #define ARM_CPUID_ARM926 0x41069265 +#define ARM_CPUID_ARM946 0x41059461 #define ARM_CPUID_PXA250 0x69052100 #define ARM_CPUID_PXA255 0x69052d00 #define ARM_CPUID_PXA260 0x69052903 |