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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:51 +0100
commit68fdb6c5b0b93d6780255d4f82940d7b342079bd (patch)
tree00419034e492961431520f5e4714ef293a9a3606 /target-arm/cpu.h
parentd81c519c40a24a49c96522a0deb834cdde264d77 (diff)
target-arm: c12_vbar -> vbar_el[]
No functional change. Preparation for adding EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-9-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a3cf37527b..62d85ff780 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t c12_vbar; /* vector base address register */
+ uint64_t vbar_el[2]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */