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authorPeter Maydell <peter.maydell@linaro.org>2014-01-04 22:15:45 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-01-07 19:17:59 +0000
commitb0d2b7d0f084f6b33acf7c722790da683916fee3 (patch)
treeb54464113094ead3227aa55fde63c3de0aba7358 /target-arm/cpu.h
parentfea505221eaf87889000378d4d33ad0dfd5f4d9d (diff)
target-arm: A64: Implement minimal set of EL0-visible sysregs
Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b09142693b..ab8ef17862 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -660,7 +660,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_CP_IO 64
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
-#define ARM_LAST_SPECIAL ARM_CP_WFI
+#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
+#define ARM_LAST_SPECIAL ARM_CP_NZCV
/* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff
/* Mask of only the flag bits in a type field */