diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:02 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:02 +0000 |
| commit | 8af35c37d296daa463c0d4ed575a51729afc7f6d (patch) | |
| tree | d21566fd97944ba61550d402dc2ee83161c710e2 /target-arm/cpu.c | |
| parent | cd4da6317748e3ae2bed5fcc5fb3f81e5c853446 (diff) | |
target-arm: Implement AArch64 cache invalidate/clean ops
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8fed098842..2f949437fd 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -91,8 +91,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 */ - env->cp15.c1_sys |= SCTLR_UCT; + /* Userspace expects access to CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; #else env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F | PSTATE_MODE_EL1h; |