diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
| commit | 14e5f106073d67e5a00a8f29a017550b0436bde8 (patch) | |
| tree | 6f811bade185b1d24ccd5668212304f12e67a551 /target-arm/cpu.c | |
| parent | 211b016915210e2b860d495f2573cfe85ec2a5d1 (diff) | |
target-arm: Correct sense of the DCZID DZP bit
The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.
To avoid this regressing the behaviour of the user-mode
emulator, we must set the DZE bit in the SCTLR for that
config so that userspace continues to see DZP as zero (it
was getting the correct result by accident previously).
Reported-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1412959792-20708-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e837f64538..e0b82a6704 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -108,8 +108,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 and the cache ops */ - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else |