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author | Ian Campbell <ijc@hellion.org.uk> | 2014-06-09 15:43:23 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-09 16:06:11 +0100 |
commit | d615efac7c4dc0984de31791c5c7d6b06408aadb (patch) | |
tree | 67c5dea7fb5be28d91bb92c80428ba354ba67051 /target-arm/cpu.c | |
parent | 8d5c773e323b22402abdd0beef4c7d2fc91dd0eb (diff) |
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.
Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.
This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Claudio Fontana <claudio.fontana@huawei.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
0 files changed, 0 insertions, 0 deletions