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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:04 +0100 |
| commit | aca3f40b374428e9c01068cf96294483cbb760a0 (patch) | |
| tree | ea0528c089b29a84a44cac1cd539d80917e51308 /target-arm/cpu-qom.h | |
| parent | 9225d739e7f6ec8d2139f79c3d2e3282cc725364 (diff) | |
target-arm: A64: Implement DC ZVA
Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
| -rw-r--r-- | target-arm/cpu-qom.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 00234e1d3d..41caa6c780 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -150,6 +150,8 @@ typedef struct ARMCPU { uint32_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ + uint32_t dcz_blocksize; } ARMCPU; #define TYPE_AARCH64_CPU "aarch64-cpu" |