aboutsummaryrefslogtreecommitdiff
path: root/target-arm/cpu-qom.h
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2015-08-13 11:26:22 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-08-13 11:26:22 +0100
commitb4d3978c2fdf944e428a46d2850dbd950b6fbe78 (patch)
treecad66422e4c81b720274cec302bcc5eda6c471af /target-arm/cpu-qom.h
parent49a661910c1374858602a3002b67115893673c25 (diff)
target-arm: Add the AArch64 view of the Secure physical timer
On CPUs with EL3, there are two physical timers, one for Secure and one for Non-secure. Implement this extra timer and the AArch64 registers which access it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 54db337675..00c0716f7d 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -225,6 +225,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
+void arm_gt_stimer_cb(void *opaque);
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);