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authorPeter Maydell <peter.maydell@linaro.org>2012-04-20 17:58:31 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-04-21 18:06:27 +0000
commit777dc78411865f2721f8728c71edb0b215da57fc (patch)
tree35e11ac4bf8594915cc1af3921cacb80c2b41c0f /target-arm/cpu-qom.h
parentce854d7cc3ba71e8d2a97e1fb33e13ac3283cbd4 (diff)
target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation. Let arm_cpu_list() enumerate CPU subclasses in alphabetical order, except for special value "any". Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID (aka MIDR, Main ID Register) value in the class. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 42d2a6b63b..a4bcb31d47 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -58,6 +58,18 @@ typedef struct ARMCPU {
/*< public >*/
CPUARMState env;
+
+ /* The instance init functions for implementation-specific subclasses
+ * set these fields to specify the implementation-dependent values of
+ * various constant registers and reset values of non-constant
+ * registers.
+ * Some of these might become QOM properties eventually.
+ * Field names match the official register names as defined in the
+ * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
+ * is used for reset values of non-constant registers; no reset_
+ * prefix means a constant register.
+ */
+ uint32_t midr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)