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authorAndreas Färber <afaerber@suse.de>2013-08-26 18:14:44 +0200
committerAndreas Färber <afaerber@suse.de>2014-03-13 19:20:47 +0100
commit0429a9719551a4aa794051aeb8c7b42658902c27 (patch)
treebfa20765bf5ae7e9fe44b8273abcd72533eebefe /target-arm/arm-semi.c
parent27103424c40ce71053c07d8a54ef431365fa9b7f (diff)
cpu: Move opaque field from CPU_COMMON to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/arm-semi.c')
-rw-r--r--target-arm/arm-semi.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index ee469c49c5..ebb5235521 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
#ifdef CONFIG_USER_ONLY
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
#endif
if (ret == (target_ulong)-1) {
@@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
env->regs[0] = be32_to_cpu(size);
#ifdef CONFIG_USER_ONLY
- ((TaskState *)env->opaque)->swi_errno = err;
+ ((TaskState *)cs->opaque)->swi_errno = err;
#else
syscall_err = err;
#endif
@@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
uint32_t do_arm_semihosting(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
char * s;
@@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
uint32_t ret;
uint32_t len;
#ifdef CONFIG_USER_ONLY
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
#else
CPUARMState *ts = env;
#endif
@@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
exit(0);
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
- cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
}