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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-16 22:44:17 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-16 22:44:17 +0000
commit6ba8dcd773e01dc3f61b3e788a8b6f12fb8ed4de (patch)
tree06d196ff232a8ec314ca4957894a1fa5b1933019 /target-alpha
parent30c7183b676076c940538b838c330c854a7995a9 (diff)
target-alpha: fix TCG register names
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-alpha')
-rw-r--r--target-alpha/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 54fe986ce0..4143076dda 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -54,7 +54,7 @@ static TCGv cpu_pc;
static TCGv cpu_T[3];
/* register names */
-static char cpu_reg_names[5*31];
+static char cpu_reg_names[10*4+21*5];
#include "gen-icount.h"
@@ -87,7 +87,7 @@ static void alpha_translate_init(void)
sprintf(p, "ir%d", i);
cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
offsetof(CPUState, ir[i]), p);
- p += 4;
+ p += (i < 10) ? 4 : 5;
}
cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,