diff options
author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2013-12-17 14:05:40 +1000 |
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committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-02-11 22:57:00 +1000 |
commit | 2c17449b3022ca9623c4a7e2a504a4150ac4ad30 (patch) | |
tree | 2d40d6a844c6116673776a8de73e2d0de28fc6ed /target-alpha | |
parent | fdfba1a298ae26dd44bcfdb0429314139a0bc55a (diff) |
exec: Make ldq/ldub_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-alpha')
-rw-r--r-- | target-alpha/helper.c | 7 | ||||
-rw-r--r-- | target-alpha/helper.h | 2 | ||||
-rw-r--r-- | target-alpha/mem_helper.c | 11 | ||||
-rw-r--r-- | target-alpha/translate.c | 2 |
4 files changed, 13 insertions, 9 deletions
diff --git a/target-alpha/helper.c b/target-alpha/helper.c index fc61bb02f7..025fdaf4d1 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -213,6 +213,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { + CPUState *cs = ENV_GET_CPU(env); target_long saddr = addr; target_ulong phys = 0; target_ulong L1pte, L2pte, L3pte; @@ -251,7 +252,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L1 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; - L1pte = ldq_phys(pt + index*8); + L1pte = ldq_phys(cs->as, pt + index*8); if (unlikely((L1pte & PTE_VALID) == 0)) { ret = MM_K_TNV; @@ -264,7 +265,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L2 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff; - L2pte = ldq_phys(pt + index*8); + L2pte = ldq_phys(cs->as, pt + index*8); if (unlikely((L2pte & PTE_VALID) == 0)) { ret = MM_K_TNV; @@ -277,7 +278,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L3 page table read. */ index = (addr >> TARGET_PAGE_BITS) & 0x3ff; - L3pte = ldq_phys(pt + index*8); + L3pte = ldq_phys(cs->as, pt + index*8); phys = L3pte >> 32 << TARGET_PAGE_BITS; if (unlikely((L3pte & PTE_VALID) == 0)) { diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 39777026de..74dbd077a8 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -102,7 +102,7 @@ DEF_HELPER_2(hw_ret, void, env, i64) DEF_HELPER_3(call_pal, void, env, i64, i64) DEF_HELPER_2(ldl_phys, i64, env, i64) -DEF_HELPER_1(ldq_phys, i64, i64) +DEF_HELPER_2(ldq_phys, i64, env, i64) DEF_HELPER_2(ldl_l_phys, i64, env, i64) DEF_HELPER_2(ldq_l_phys, i64, env, i64) DEF_HELPER_2(stl_phys, void, i64, i64) diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 61e81644a2..5b47b041f5 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -30,9 +30,10 @@ uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p) return (int32_t)ldl_phys(cs->as, p); } -uint64_t helper_ldq_phys(uint64_t p) +uint64_t helper_ldq_phys(CPUAlphaState *env, uint64_t p) { - return ldq_phys(p); + CPUState *cs = ENV_GET_CPU(env); + return ldq_phys(cs->as, p); } uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p) @@ -44,8 +45,9 @@ uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p) uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p) { + CPUState *cs = ENV_GET_CPU(env); env->lock_addr = p; - return env->lock_value = ldq_phys(p); + return env->lock_value = ldq_phys(cs->as, p); } void helper_stl_phys(uint64_t p, uint64_t v) @@ -77,10 +79,11 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) { + CPUState *cs = ENV_GET_CPU(env); uint64_t ret = 0; if (p == env->lock_addr) { - uint64_t old = ldq_phys(p); + uint64_t old = ldq_phys(cs->as, p); if (old == env->lock_value) { stq_phys(p, v); ret = 1; diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 802c49a5d7..f60ee356f1 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2916,7 +2916,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) break; case 0x1: /* Quadword physical access (hw_ldq/p) */ - gen_helper_ldq_phys(cpu_ir[ra], addr); + gen_helper_ldq_phys(cpu_ir[ra], cpu_env, addr); break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ |