diff options
| author | Richard Henderson <rth@twiddle.net> | 2010-04-07 10:17:24 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-04-27 05:50:41 +0200 |
| commit | 593f17e5f2125a7186a4a1917cb8603ffb636d48 (patch) | |
| tree | ea445cfc6feee3d4e107b37e8d6b6f271e72fa61 /target-alpha/translate.c | |
| parent | ac316ca4b7b27c853c0d9d6b43abdbefc97297d6 (diff) | |
target-alpha: Implement cvtlq inline.
It's a simple shift and mask sequence.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-alpha/translate.c')
| -rw-r--r-- | target-alpha/translate.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 1c296cfbb4..d7591cc9bd 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -598,6 +598,28 @@ static inline void gen_fp_exc_raise(int rc, int fn11) gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact); } +static void gen_fcvtlq(int rb, int rc) +{ + if (unlikely(rc == 31)) { + return; + } + if (unlikely(rb == 31)) { + tcg_gen_movi_i64(cpu_fir[rc], 0); + } else { + TCGv tmp = tcg_temp_new(); + + /* The arithmetic right shift here, plus the sign-extended mask below + yields a sign-extended result without an explicit ext32s_i64. */ + tcg_gen_sari_i64(tmp, cpu_fir[rb], 32); + tcg_gen_shri_i64(cpu_fir[rc], cpu_fir[rb], 29); + tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000); + tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rc], 0x3fffffff); + tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); + + tcg_temp_free(tmp); + } +} + static void gen_fcvtql(int rb, int rc) { if (unlikely(rc == 31)) { @@ -647,7 +669,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \ tcg_temp_free(tmp); \ } \ } -FARITH2(cvtlq) /* ??? VAX instruction qualifiers ignored. */ FARITH2(sqrtf) |