diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:52:03 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:29 +0000 |
| commit | 962415fcd5f8223a6fbc6f7bb8c5fdf2500f2f84 (patch) | |
| tree | 2e87691b27555e8ceab0e0fa7dc6249467013f6a /target-alpha/translate.c | |
| parent | f1fae40c61fd4558c7d10992c98b4bb47f99e0ed (diff) | |
target-alpha: Use mulu2 for umulh insn
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-alpha/translate.c')
| -rw-r--r-- | target-alpha/translate.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index f687b95c63..f8f76957a9 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1390,7 +1390,6 @@ static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\ tcg_temp_free(tmp1); \ } \ } -ARITH3(umulh) ARITH3(cmpbge) ARITH3(minub8) ARITH3(minsb8) @@ -2426,7 +2425,24 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) break; case 0x30: /* UMULH */ - gen_umulh(ra, rb, rc, islit, lit); + { + TCGv low; + if (unlikely(rc == 31)){ + break; + } + if (ra == 31) { + tcg_gen_movi_i64(cpu_ir[rc], 0); + break; + } + low = tcg_temp_new(); + if (islit) { + tcg_gen_movi_tl(low, lit); + tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], low); + } else { + tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); + } + tcg_temp_free(low); + } break; case 0x40: /* MULL/V */ |