diff options
| author | Richard Henderson <rth@twiddle.net> | 2010-04-12 16:14:54 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-04-27 05:50:41 +0200 |
| commit | ac316ca4b7b27c853c0d9d6b43abdbefc97297d6 (patch) | |
| tree | fb93c58e301dd4cdd40fd29e24e06313853daf79 /target-alpha/translate.c | |
| parent | dc96be4b975d51f03d0b08e191fddf85b92c0267 (diff) | |
target-alpha: Implement rs/rc properly.
This is a per-cpu flag; there's no need for a spinlock of any kind.
We were also failing to manipulate the flag with $31 as a target reg
and failing to clear the flag on execution of a return-from-interrupt
instruction.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-alpha/translate.c')
| -rw-r--r-- | target-alpha/translate.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 96d876b56b..1c296cfbb4 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1301,6 +1301,19 @@ static void gen_cmp(TCGCond cond, int ra, int rb, int rc, } } +static void gen_rx(int ra, int set) +{ + TCGv_i32 tmp; + + if (ra != 31) { + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag)); + } + + tmp = tcg_const_i32(set); + tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag)); + tcg_temp_free_i32(tmp); +} + static inline int translate_one(DisasContext *ctx, uint32_t insn) { uint32_t palcode; @@ -2392,16 +2405,14 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0xE000: /* RC */ - if (ra != 31) - gen_helper_rc(cpu_ir[ra]); + gen_rx(ra, 0); break; case 0xE800: /* ECB */ break; case 0xF000: /* RS */ - if (ra != 31) - gen_helper_rs(cpu_ir[ra]); + gen_rx(ra, 1); break; case 0xF800: /* WH64 */ |