diff options
| author | Richard Henderson <rth@twiddle.net> | 2011-04-18 15:09:09 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@anchor.twiddle.net> | 2011-05-31 10:18:05 -0700 |
| commit | 6a80e088c70b88f844ed90b78f4ce987c43ec522 (patch) | |
| tree | 71da5cd011715a126943b47903a684ef553e2c4e /target-alpha/exec.h | |
| parent | a18ad89351dd6c828b7fe33fafd1764cef61a40d (diff) | |
target-alpha: Disable interrupts properly.
Interrupts are disabled in PALmode, and when the PS IL is high enough.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha/exec.h')
| -rw-r--r-- | target-alpha/exec.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 6ae96d148b..7a325e7a75 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -39,7 +39,17 @@ register struct CPUAlphaState *env asm(AREG0); static inline int cpu_has_work(CPUState *env) { - return (env->interrupt_request & CPU_INTERRUPT_HARD); + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return env->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |