diff options
author | Richard Henderson <rth@twiddle.net> | 2011-04-18 12:17:02 -0700 |
---|---|---|
committer | Richard Henderson <rth@anchor.twiddle.net> | 2011-05-31 10:18:04 -0700 |
commit | 352e48b0f492359559cb46f8b3222bac9c461ac4 (patch) | |
tree | 8b6bb312ae0d46ff3933c0ab4ad2c7ef8e3a2c24 /target-alpha/cpu.h | |
parent | bf1b03fe182eb5a0df9ec6fc4121d8a36e1fdb97 (diff) |
target-alpha: Remove partial support for palcode emulation.
This code does not work, and will be replaced by a bios image.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha/cpu.h')
-rw-r--r-- | target-alpha/cpu.h | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 686fb4a6a7..0daa5563ec 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -319,36 +319,6 @@ enum { typedef struct CPUAlphaState CPUAlphaState; -typedef struct pal_handler_t pal_handler_t; -struct pal_handler_t { - /* Reset */ - void (*reset)(CPUAlphaState *env); - /* Uncorrectable hardware error */ - void (*machine_check)(CPUAlphaState *env); - /* Arithmetic exception */ - void (*arithmetic)(CPUAlphaState *env); - /* Interrupt / correctable hardware error */ - void (*interrupt)(CPUAlphaState *env); - /* Data fault */ - void (*dfault)(CPUAlphaState *env); - /* DTB miss pal */ - void (*dtb_miss_pal)(CPUAlphaState *env); - /* DTB miss native */ - void (*dtb_miss_native)(CPUAlphaState *env); - /* Unaligned access */ - void (*unalign)(CPUAlphaState *env); - /* ITB miss */ - void (*itb_miss)(CPUAlphaState *env); - /* Instruction stream access violation */ - void (*itb_acv)(CPUAlphaState *env); - /* Reserved or privileged opcode */ - void (*opcdec)(CPUAlphaState *env); - /* Floating point exception */ - void (*fen)(CPUAlphaState *env); - /* Call pal instruction */ - void (*call_pal)(CPUAlphaState *env, uint32_t palcode); -}; - #define NB_MMU_MODES 4 struct CPUAlphaState { @@ -393,7 +363,6 @@ struct CPUAlphaState { uint32_t features; uint32_t amask; int implver; - pal_handler_t *pal_handler; }; #define cpu_init cpu_alpha_init @@ -506,10 +475,6 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); -#if !defined (CONFIG_USER_ONLY) -void pal_init (CPUState *env); -void call_pal (CPUState *env); -#endif static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) |