diff options
author | Andreas Färber <afaerber@suse.de> | 2013-08-25 18:53:55 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2014-03-13 19:01:49 +0100 |
commit | 8c2e1b0093aa4a89548df47d969217d8b0dfd070 (patch) | |
tree | 16656127c1a0c6194b25f29bd54f612b9c1f8679 /target-alpha/cpu.c | |
parent | 1cf5ccbca8915277098727d900d52c495a711f88 (diff) |
cpu: Turn cpu_has_work() into a CPUClass hook
Default to false.
Tidy variable naming and inline cast uses while at it.
Tested-by: Jia Liu <proljc@gmail.com> (or32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-alpha/cpu.c')
-rw-r--r-- | target-alpha/cpu.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index a0d5d5bd93..cf2a3156d1 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -31,6 +31,21 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +static bool alpha_cpu_has_work(CPUState *cs) +{ + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return cs->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); +} + static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -267,6 +282,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) dc->realize = alpha_cpu_realizefn; cc->class_by_name = alpha_cpu_class_by_name; + cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; |