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authorPeter Maydell <peter.maydell@linaro.org>2024-02-14 15:45:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-02-14 15:45:52 +0000
commit5767815218efd3cbfd409505ed824d5f356044ae (patch)
tree3451522a0e9f8fc03fa5d0af14cdf1ff259a2ab0 /system
parent708322660e15e83a37fb6deb8470209307ef43a2 (diff)
parent1dd6954c3f5c5c610cf94b6f740118e565957293 (diff)
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, cleanups, fixes vhost-user-snd support x2APIC mode with TCG support CXL update to r3.1 fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmXMoXUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpFtMIAKUKD0hzJrwOyPo4xsRUMbsB3ehIsJsMKfOK # w+JWzTaojAG8ENPelWBdL2sEIs5U73VOchjLqHbH2m5sz6GJ13214amvdU/fYc8+ # /dU2ZKoAmaR5L1ovKO/fq07y/J6DrITZ5tosy2i84Xa8EnsL4j3wEPNVWsDi7dna # mvXUICSOOoJQ4O2YhSruKCQ8qIgF1/0Oi3u/rcrW3alSs8VQlrtQXxl6k+LbYqek # +Fytco3jMRHPvQ+GYUIwGuHjN15ghArcvbsV0GIa+24BPY5h7YbDYGbfasePT5OK # zDz51jitkoyDrQr+OzwOEe/X5+dVGhayRXfMtU5Qm53IE3y61qc= # =K4b1 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Feb 2024 11:18:13 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (60 commits) MAINTAINERS: Switch to my Enfabrica email virtio-gpu-rutabaga.c: override resource_destroy method virtio-gpu.c: add resource_destroy class method hw/display/virtio-gpu.c: use reset_bh class method hw/smbios: Fix port connector option validation hw/smbios: Fix OEM strings table option validation virtio-gpu: Correct virgl_renderer_resource_get_info() error check hw/cxl: Standardize all references on CXL r3.1 and minor updates hw/cxl: Update mailbox status registers. hw/cxl: Update RAS Capability Definitions for version 3. hw/cxl: Update link register definitions. hw/cxl: Update HDM Decoder capability to version 3 tests/acpi: Update DSDT.cxl to reflect change _STA return value. hw/i386: Fix _STA return value for ACPI0017 tests/acpi: Allow update of DSDT.cxl hw/mem/cxl_type3: Fix potential divide by zero reported by coverity hw/cxl: Pass NULL for a NULL MemoryRegionOps hw/cxl: Pass CXLComponentState to cache_mem_ops hw/cxl/device: read from register values in mdev_reg_read() hw/cxl/mbox: Remove dead code ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'system')
-rw-r--r--system/ioport.c41
1 files changed, 34 insertions, 7 deletions
diff --git a/system/ioport.c b/system/ioport.c
index 1824aa808c..fd551d0375 100644
--- a/system/ioport.c
+++ b/system/ioport.c
@@ -133,6 +133,7 @@ void portio_list_init(PortioList *piolist,
piolist->nr = 0;
piolist->regions = g_new0(MemoryRegion *, n);
piolist->address_space = NULL;
+ piolist->addr = 0;
piolist->opaque = opaque;
piolist->owner = owner;
piolist->name = name;
@@ -181,13 +182,13 @@ static uint64_t portio_read(void *opaque, hwaddr addr, unsigned size)
data = ((uint64_t)1 << (size * 8)) - 1;
if (mrp) {
- data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
+ data = mrp->read(mrpio->portio_opaque, mrpio->mr.addr + addr);
} else if (size == 2) {
mrp = find_portio(mrpio, addr, 1, false);
if (mrp) {
- data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
+ data = mrp->read(mrpio->portio_opaque, mrpio->mr.addr + addr);
if (addr + 1 < mrp->offset + mrp->len) {
- data |= mrp->read(mrpio->portio_opaque, mrp->base + addr + 1) << 8;
+ data |= mrp->read(mrpio->portio_opaque, mrpio->mr.addr + addr + 1) << 8;
} else {
data |= 0xff00;
}
@@ -203,13 +204,13 @@ static void portio_write(void *opaque, hwaddr addr, uint64_t data,
const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, true);
if (mrp) {
- mrp->write(mrpio->portio_opaque, mrp->base + addr, data);
+ mrp->write(mrpio->portio_opaque, mrpio->mr.addr + addr, data);
} else if (size == 2) {
mrp = find_portio(mrpio, addr, 1, true);
if (mrp) {
- mrp->write(mrpio->portio_opaque, mrp->base + addr, data & 0xff);
+ mrp->write(mrpio->portio_opaque, mrpio->mr.addr + addr, data & 0xff);
if (addr + 1 < mrp->offset + mrp->len) {
- mrp->write(mrpio->portio_opaque, mrp->base + addr + 1, data >> 8);
+ mrp->write(mrpio->portio_opaque, mrpio->mr.addr + addr + 1, data >> 8);
}
}
}
@@ -244,7 +245,6 @@ static void portio_list_add_1(PortioList *piolist,
/* Adjust the offsets to all be zero-based for the region. */
for (i = 0; i < count; ++i) {
mrpio->ports[i].offset -= off_low;
- mrpio->ports[i].base = start + off_low;
}
/*
@@ -283,6 +283,7 @@ void portio_list_add(PortioList *piolist,
unsigned int off_low, off_high, off_last, count;
piolist->address_space = address_space;
+ piolist->addr = start;
/* Handle the first entry specially. */
off_last = off_low = pio_start->offset;
@@ -323,6 +324,32 @@ void portio_list_del(PortioList *piolist)
}
}
+void portio_list_set_enabled(PortioList *piolist, bool enabled)
+{
+ unsigned i;
+
+ for (i = 0; i < piolist->nr; ++i) {
+ memory_region_set_enabled(piolist->regions[i], enabled);
+ }
+}
+
+void portio_list_set_address(PortioList *piolist, uint32_t addr)
+{
+ MemoryRegionPortioList *mrpio;
+ unsigned i, j;
+
+ for (i = 0; i < piolist->nr; ++i) {
+ mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
+ memory_region_set_address(&mrpio->mr,
+ mrpio->mr.addr - piolist->addr + addr);
+ for (j = 0; mrpio->ports[j].size; ++j) {
+ mrpio->ports[j].offset += addr - piolist->addr;
+ }
+ }
+
+ piolist->addr = addr;
+}
+
static void memory_region_portio_list_finalize(Object *obj)
{
MemoryRegionPortioList *mrpio = MEMORY_REGION_PORTIO_LIST(obj);