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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-11-01 11:21:02 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-11-01 11:21:02 +0000 |
| commit | bf99fd3983d7185178a0f65ce29bb94b1aecaed1 (patch) | |
| tree | 8663962d1a07705404c33eb0572caeb690fd66d7 /slirp/slirp_config.h | |
| parent | 0e356366516b9e1f8cb03945d1ce72e8e0751fb0 (diff) | |
| parent | 5a7267b6a9e94c264ca77a7ca5a239e70dac81da (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-sparc-20161031-2' into staging
target-sparc updates for atomics and alignment
# gpg: Signature made Mon 31 Oct 2016 20:47:57 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-sparc-20161031-2:
target-sparc: Use tcg_gen_atomic_cmpxchg_tl
target-sparc: Use tcg_gen_atomic_xchg_tl
target-sparc: Remove MMU_MODE*_SUFFIX
target-sparc: Allow 4-byte alignment on fp mem ops
target-sparc: Implement ldqf and stqf inline
target-sparc: Remove asi helper code handled inline
target-sparc: Implement BCOPY/BFILL inline
target-sparc: Implement cas_asi/casx_asi inline
target-sparc: Implement ldstub_asi inline
target-sparc: Implement swap_asi inline
target-sparc: Handle more twinx asis
target-sparc: Use MMU_PHYS_IDX for bypass asis
target-sparc: Add MMU_PHYS_IDX
target-sparc: Introduce cpu_raise_exception_ra
target-sparc: Use overalignment flags for twinx and block asis
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'slirp/slirp_config.h')
0 files changed, 0 insertions, 0 deletions