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author | Vitaly Chipounov <vitaly.chipounov@epfl.ch> | 2012-07-03 00:20:49 +0200 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-29 08:45:57 +0000 |
commit | 7162ab21fe8e82f924002951cd8e87f69358f8b5 (patch) | |
tree | 97bac741e500dac066d88c33c309b8fe73cac340 /slirp/bootp.h | |
parent | e6d91ab66bad2bce9319fe8b0011f765042a7bb2 (diff) |
x86: Fixed incorrect segment base address addition in 64-bits mode
According to the Intel manual
"Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3", "3.4.4 Segment Loading Instructions in IA-32e Mode":
"When in compatibility mode, FS and GS overrides operate as defined by
32-bit mode behavior regardless of the value loaded into the upper 32
linear-address bits of the hidden descriptor register base field.
Compatibility mode ignores the upper 32 bits when calculating an effective address."
However, the code misses the 64-bit mode case, where an instruction with
address and segment size override would be translated incorrectly. For example,
inc dword ptr gs:260h[ebx*4] gets incorrectly translated to:
(uint32_t)(gs.base + ebx * 4 + 0x260)
instead of
gs.base + (uint32_t)(ebx * 4 + 0x260)
Signed-off-by: Vitaly Chipounov <vitaly.chipounov@epfl.ch>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'slirp/bootp.h')
0 files changed, 0 insertions, 0 deletions