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author | Anthony Liguori <aliguori@us.ibm.com> | 2012-06-03 07:56:23 +0800 |
---|---|---|
committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-06-03 07:56:23 +0800 |
commit | 74f4d2279b12a970d499558e4c38421724777827 (patch) | |
tree | 150f8f711770974b31c5f0e086228d725f75ed7d /scripts | |
parent | 2eb02f28269dc47b38aa3becbaff1cc6300210da (diff) | |
parent | 7d37d351dffee60fc7048bbfd8573421f15eb724 (diff) |
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
* qemu-kvm/uq/master:
virtio/vhost: Add support for KVM in-kernel MSI injection
msix: Add msix_nr_vectors_allocated
kvm: Enable use of kvm_irqchip_in_kernel in hwlib code
kvm: Introduce kvm_irqchip_add/remove_irqfd
kvm: Make kvm_irqchip_commit_routes an internal service
kvm: Publicize kvm_irqchip_release_virq
kvm: Introduce kvm_irqchip_add_msi_route
kvm: Rename kvm_irqchip_add_route to kvm_irqchip_add_irq_route
msix: Introduce vector notifiers
msix: Invoke msix_handle_mask_update on msix_mask_all
msix: Factor out msix_get_message
kvm: update vmxcap for EPT A/D, INVPCID, RDRAND, VMFUNC
kvm: Enable in-kernel irqchip support by default
kvm: Add support for direct MSI injections
kvm: Update kernel headers
kvm: x86: Wire up MSI support for in-kernel irqchip
pc: Enable MSI support at APIC level
kvm: Introduce basic MSI support for in-kernel irqchips
Introduce MSIMessage structure
kvm: Refactor KVMState::max_gsi to gsi_count
Diffstat (limited to 'scripts')
-rwxr-xr-x | scripts/kvm/vmxcap | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap index a74ce71917..cbe6440ba3 100755 --- a/scripts/kvm/vmxcap +++ b/scripts/kvm/vmxcap @@ -22,6 +22,7 @@ MSR_IA32_VMX_TRUE_PINBASED_CTLS = 0x48D MSR_IA32_VMX_TRUE_PROCBASED_CTLS = 0x48E MSR_IA32_VMX_TRUE_EXIT_CTLS = 0x48F MSR_IA32_VMX_TRUE_ENTRY_CTLS = 0x490 +MSR_IA32_VMX_VMFUNC = 0x491 class msr(object): def __init__(self): @@ -147,6 +148,9 @@ controls = [ 6: 'WBINVD exiting', 7: 'Unrestricted guest', 10: 'PAUSE-loop exiting', + 11: 'RDRAND exiting', + 12: 'Enable INVPCID', + 13: 'Enable VM functions', }, cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2, ), @@ -193,6 +197,7 @@ controls = [ 8: 'Wait-for-SIPI activity state', (16,24): 'Number of CR3-target values', (25,27): 'MSR-load/store count recommenation', + 28: 'IA32_SMM_MONITOR_CTL[2] can be set to 1', (32,62): 'MSEG revision identifier', }, msr = MSR_IA32_VMX_MISC_CTLS, @@ -208,6 +213,7 @@ controls = [ 16: '2MB EPT pages', 17: '1GB EPT pages', 20: 'INVEPT supported', + 21: 'EPT accessed and dirty flags', 25: 'Single-context INVEPT', 26: 'All-context INVEPT', 32: 'INVVPID supported', @@ -218,6 +224,13 @@ controls = [ }, msr = MSR_IA32_VMX_EPT_VPID_CAP, ), + Misc( + name = 'VM Functions', + bits = { + 0: 'EPTP Switching', + }, + msr = MSR_IA32_VMX_VMFUNC, + ), ] for c in controls: |