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authorAlistair Francis <alistair.francis@wdc.com>2020-01-20 21:36:57 -0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-03-16 17:03:13 -0700
commited5abf46b3c414ef58e647145f19b3966700b206 (patch)
tree118e2d70b680eda5c99f5ecdc0c43414988b8f4c /roms
parenta98135f727595382e200d04c2996e868b7925a01 (diff)
target/riscv: Correctly implement TSR trap
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <jonathan@fintelia.io Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'roms')
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