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authorPeter Maydell <peter.maydell@linaro.org>2012-04-13 11:39:07 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-04-13 11:39:07 +0000
commit544d1afa7013fce155f5afbbc24737f2fc0c0f26 (patch)
tree28750d0864852d6bd7023f5f36586a1bf6581188 /qfloat.h
parent926c4aff6ecf2b26b3508773196314a774bf5c4c (diff)
hw/arm_gic: Expose PPI inputs as gpio inputs
Expose the Private Peripheral Interrupt inputs as GPIO inputs. The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ... Treating PPIs as being another kind of input line is in line with the GIC architecture specification, where they are clearly described that way. The 11MPCore TRM is a bit more ambiguous, but there is no practical difference between "set PPI X as pending" and "0->1 transition on a PPI input line configured as edge triggered", and PPIs are always edge triggered, so this change won't affect behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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