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authorCédric Le Goater <clg@kaod.org>2016-10-22 11:46:38 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2016-10-28 09:38:25 +1100
commit631adaff31d9e127fecccb4a811c20ae13cd7194 (patch)
treef1b9498ab9ca86aede63c40d2ccd7149923a340c /qemu-nbd.c
parent397a79e7575c4ea98507ff9d1d2629b58725d484 (diff)
ppc/pnv: add a PIR handler to PnvChip
The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9 and P8 have some differences in the CPU PIR encoding. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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