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authorStefan Hajnoczi <stefanha@redhat.com>2022-10-03 15:00:36 -0400
committerStefan Hajnoczi <stefanha@redhat.com>2022-10-03 15:00:36 -0400
commit81f12b8cdfb6ea526c57a2d367ea6424f16c3106 (patch)
tree5185b14ba6bf106dcac6010f2ef5969b10f2594b /qemu-io.c
parent539cb0876b0a84731267d6a21cd3448f87c9ae62 (diff)
parentbeeec926d24aac28f95cc7694ef3837d7a4cd3bb (diff)
Merge tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 * Make writes to MDCR_EL3 use PMU start/finish calls * Let AArch32 write to SDCR.SCCD * Rearrange cpu64.c so all the CPU initfns are together * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers * hw/arm/virt: fix some minor issues with generated device tree * Fix regression where EL3 could not write to SP_EL1 if there is no EL2 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmM28EYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mw9D/44e72KHZdfr3F/Cmd0Jku2 # g5NQ4ooKV90rY4Y4+/VR9Z2k7a72lWFgFl7/54AKXSZsZSmNomeh2WxWJAs1lA2W # 4rmGPlLwxZYMQumYcMOArYxJQgRK5exVtE6ECKM/JERjhKSbnL1lyLWGUyLtFJfq # SjxoTWEigPHu+0fX/nk04rFzrA6Bo1qKQqZZTuN9zcT6JXyQMjZNF89Fxy9OlV4s # dlOXsZILV8oREnGdDFPYLgwSTMn+1rrD8xfjK/DTQrlUVX/9zhlIeKg5O4JadxCy # 8ThIFCyODUanlRvyjHiwvcvStHn8wwyCp4uJrxmZGyyp4t4u3etG0hpsZaPtiN9O # NKtad4Aoc6lSmIDhYYZA1LIIdSIeyUPD/LyWTd+qKK7A7mxH6ORr0uyjhb01jWs3 # ceyne1i0n66oRLbHxPyjQEkLqwLl2CsqWr41BNM5RVoYjCU8HYSvEwlh7t+EZCL5 # IRkfAWJkA9bdXL30ZmYSzJ7hfvVkWhDsHD+eOzAcsxoApgzI5Mfi7gCIZ+LNY20P # W0akGbA6l0InsmIcBpyXEztPOi6tOD/J55qeOCrzHjgfhoJWCoa/mS8bVqN0mKIA # yJ7QbiK/JY6+G1v2oM8aARLn8/C7oLnMYiKntXNBMj67Ry5GwjDt+A37MUHgQbZb # yUzUjr3O2N1qJRKi+Dd7eA== # =edYy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 30 Sep 2022 09:33:58 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP hw/arm/virt: Fix devicetree warning about the SMMU node hw/arm/virt: Use "msi-map" devicetree property for PCI hw/arm/virt: Fix devicetree warning about the GIC node hw/arm/virt: Fix devicetree warning about the root node hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers target/arm: Rearrange cpu64.c so all the CPU initfns are together target/arm: Update SDCR_VALID_MASK to include SCCD target/arm: Make writes to MDCR_EL3 use PMU start/finish calls target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'qemu-io.c')
0 files changed, 0 insertions, 0 deletions