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authorAndrey Smirnov <andrew.smirnov@gmail.com>2018-03-15 12:11:40 -0700
committerPeter Maydell <peter.maydell@linaro.org>2018-03-19 18:23:24 +0000
commit824e4a12f3de76d3efb3229027a04c1fd69244d5 (patch)
treee8832b6ebebe020752df9bebefe88628b2a24410 /qemu-img.texi
parent68cbecfdd7afbfdf9cb06a87a2a297e8a6add7d7 (diff)
char: i.MX: Simplify imx_update()
Code of imx_update() is slightly confusing since the "flags" variable doesn't really corespond to anything in real hardware and server as a kitchensink accumulating events normally reported via USR1 and USR2 registers. Change the code to explicitly evaluate state of interrupts reported via USR1 and USR2 against corresponding masking bits and use the to detemine if IRQ line should be asserted or not. NOTE: Check for UTS1_TXEMPTY being set has been dropped for two reasons: 1. Emulation code implements a single character FIFO, so this flag will always be set since characters are trasmitted as a part of the code emulating "push" into the FIFO 2. imx_update() is really just a function doing ORing and maksing of reported events, so checking for UTS1_TXEMPTY should happen, if it's ever really needed should probably happen outside of it. Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: Bill Paul <wpaul@windriver.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qemu-img.texi')
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