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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-16 19:03:05 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-08-26 17:02:01 +0100 |
| commit | 8e228c9e4bcfea634e7ee404f4d13136d2072c71 (patch) | |
| tree | dc82dfa1366d417dd3f1fe3c6e35365104ced5b7 /os-posix.c | |
| parent | cc7613bfaa1f653a6eb6ff50ac45d5c5fd717052 (diff) | |
target/arm: Implement HSTR.TJDBX
In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1
access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ.
Implement these traps. In v8A this HSTR bit doesn't exist, so don't
trap for v8A CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-3-peter.maydell@linaro.org
Diffstat (limited to 'os-posix.c')
0 files changed, 0 insertions, 0 deletions