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authorIgor V. Kovalenko <igor.v.kovalenko@gmail.com>2010-01-07 23:28:31 +0300
committerBlue Swirl <blauwirbel@gmail.com>2010-01-08 17:25:13 +0000
commitd532b26c9dee0fb5b2186572f921b1e413963ec2 (patch)
tree75eef4cbe9034f96b98c176db0e8eeb03923f652 /net
parent2df6c2d0de31461f18d97f8a4d122bdb003297db (diff)
sparc64: interrupt trap handling
cpu_check_irqs - handle SOFTINT register TICK and STICK timer bits - only check interrupt levels greater than PIL value - handle preemption by higher level traps cpu_exec - handle CPU_INTERRUPT_HARD only if interrupts are enabled - PIL 15 is not special level on sparcv9 Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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