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authorDavid Gibson <david@gibson.dropbear.id.au>2016-01-27 11:07:29 +1100
committerDavid Gibson <david@gibson.dropbear.id.au>2016-01-30 23:37:38 +1100
commitbcd81230037f60a2fc9c2e903f8f07db68f86ce8 (patch)
treeac88c4bf9067a8fa3e89586699fa99224bd70d75 /net/tap.c
parent7ef23068bfa413605de8ae7e3e654d9198369fa8 (diff)
target-ppc: Rework ppc_store_slb
ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs. Currently it takes two parameters, which contain values encoded as the register arguments to the slbmte instruction, one register contains the ESID portion of the SLBE and also the slot number, the other contains the VSID portion of the SLBE. We're shortly going to want to do some SLB updates from other code where it is more convenient to supply the slot number and ESID separately, so rework this function and its callers to work this way. As a bonus, this slightly simplifies the emulation of segment registers for when running a 32-bit OS on a 64-bit CPU. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alexander Graf <agraf@suse.de>
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