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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:20 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:51:36 +1000 |
| commit | 308ee805786a18f236daead36b11f53cd5017899 (patch) | |
| tree | fb4209d390eddc8afbf1c4058bf8153a5b3d942c /module-common.c | |
| parent | f4f47e04de6185ddaf36e9b6ec34aa6e28923a07 (diff) | |
target/riscv: rvv-1.0: allow load element with sign-extended
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-35-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'module-common.c')
0 files changed, 0 insertions, 0 deletions