aboutsummaryrefslogtreecommitdiff
path: root/meson.build
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2020-09-13 20:29:35 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-09-13 20:29:35 +0100
commitf00f57f344236bbbe4c20845a0276a490dd5ffea (patch)
tree0b1090f44ac0480dc6e39436e59872615debb74a /meson.build
parent3d9f371b01067d9cec4d592920013012119397c8 (diff)
parent7595a65818ea9b49c36650a8c217a1ef9bd6e62a (diff)
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events
Diffstat (limited to 'meson.build')
-rw-r--r--meson.build1
1 files changed, 0 insertions, 1 deletions
diff --git a/meson.build b/meson.build
index bd84a1e777..690723b470 100644
--- a/meson.build
+++ b/meson.build
@@ -773,7 +773,6 @@ if have_system
'hw/watchdog',
'hw/xen',
'hw/gpio',
- 'hw/riscv',
'migration',
'net',
'softmmu',