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authorYifei Jiang <jiangyifei@huawei.com>2022-01-12 16:13:29 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-01-21 15:52:56 +1000
commitfbf43c7dbf18156d4dce73183dd17b83f6ca65fc (patch)
tree164eee781d3feea1c6d0d6569d04c520144e1c9f /meson.build
parent1eb9a5da31abb0a7b613756f5bb7c887b7ef60ea (diff)
target/riscv: enable riscv kvm accel
Add riscv kvm support in meson.build file. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-id: 20220112081329.1835-14-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'meson.build')
-rw-r--r--meson.build2
1 files changed, 2 insertions, 0 deletions
diff --git a/meson.build b/meson.build
index 333c61deba..833fd6bc4c 100644
--- a/meson.build
+++ b/meson.build
@@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
elif cpu in ['mips', 'mips64']
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
+elif cpu in ['riscv']
+ kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
else
kvm_targets = []
endif