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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2016-02-03 12:31:07 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-02-26 08:59:17 +0000 |
| commit | 01bc435b44b8802cc4697faa07d908684afbce4e (patch) | |
| tree | eb377fa81c980fba2f2c08941e43ba526d395041 /main-loop.c | |
| parent | bee62662a312b99b4418b558a99b3963a4cbff07 (diff) | |
target-mips: implement R6 multi-threading
MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'main-loop.c')
0 files changed, 0 insertions, 0 deletions