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authorAleksandar Rikalo <arikalo@wavecomp.com>2018-08-07 12:40:04 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2018-08-24 17:51:59 +0200
commit0b16dcd180bdbe3add9edea42c2374d427882661 (patch)
tree4bcc65246daf4513e388ae0b6a46147a89e2794e /linux-user
parentab77fc611bf004dfd25ecad5b2c11261e32012e9 (diff)
target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'linux-user')
-rw-r--r--linux-user/mips/cpu_loop.c25
1 files changed, 20 insertions, 5 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 084ad6a041..1d3dc9e913 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)
target_ulong addr;
target_ulong page_addr;
target_ulong val;
+ uint32_t val_wp = 0;
+ uint32_t llnewval_wp = 0;
int flags;
int segv = 0;
int reg;
int d;
+ int wp;
addr = env->lladdr;
page_addr = addr & TARGET_PAGE_MASK;
@@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env)
} else {
reg = env->llreg & 0x1f;
d = (env->llreg & 0x20) != 0;
- if (d) {
- segv = get_user_s64(val, addr);
+ wp = (env->llreg & 0x40) != 0;
+ if (!wp) {
+ if (d) {
+ segv = get_user_s64(val, addr);
+ } else {
+ segv = get_user_s32(val, addr);
+ }
} else {
segv = get_user_s32(val, addr);
+ segv |= get_user_s32(val_wp, addr);
+ llnewval_wp = env->llnewval_wp;
}
if (!segv) {
- if (val != env->llval) {
+ if (val != env->llval && val_wp == llnewval_wp) {
env->active_tc.gpr[reg] = 0;
} else {
- if (d) {
- segv = put_user_u64(env->llnewval, addr);
+ if (!wp) {
+ if (d) {
+ segv = put_user_u64(env->llnewval, addr);
+ } else {
+ segv = put_user_u32(env->llnewval, addr);
+ }
} else {
segv = put_user_u32(env->llnewval, addr);
+ segv |= put_user_u32(env->llnewval_wp, addr + 4);
}
if (!segv) {
env->active_tc.gpr[reg] = 1;